A typical computing system is composed of multiple processors and various memory components which may be in electrical communication with each other using different forms of intermediate mediums for interconnecting the components. One common processing system includes a central processing unit (CPU) which interacts with various components, for example, a graphics processor and input and output devices. To more effectively facilitate the transmission of information within the processing system, the CPU is coupled to an information router, such as a north bridge, which determines where to route the information. Typically, the information router, herein after referred to as the north bridge, determines whether the instruction is addressing a location within a graphics based address space, such as an accelerated graphics, a dynamic random access memory (DRAM) address space (i.e. system memory), or an input/output interface address, such as a PCI address space.
One major function of the north bridge is to direct system memory instructions from a system memory. Previously, due to size limitations of the memory devices, the north bridge was disposed on a separate integrated circuit and the system memory consisted of a dual in-line memory module (DIMM) or any other type of memory as recognized by one skilled in the art, such as, but not limited to, SDRAM or RAMBUS, hosting a plurality of memories, such as a DRAM.
In a typical north bridge processing system, if the received physical address corresponds to the AGP address space, the north bridge further translates the physical address, using a GART table, into a corresponding physical address. Having obtained the physical address, the north bridge communicates with the memory to retrieve the appropriate memory block (e.g., line of memory, or multiple lines of memory where a line is 32 bits, 64 bits, 128 bits, etc.). If the physical address corresponds to the memory, the north bridge utilizes the physical address to facilitate the memory transaction. As such, if the memory transaction was a read transaction, the north bridge facilitates the retrieval of the corresponding memory line or lines from memory and provides them to the central processing unit. If the received physical address corresponds with the PCI address space, the north bridge passes the transaction to the PCI bus.
A south bridge, upon receiving a physical address, determines which of the plurality of I/O devices is to receive the transaction. To facilitate the forwarding of transactions to the I/O devices, the south bridge includes a plurality of memories, one for each I/O device coupled thereto, for queuing transactions to and from the corresponding I/O device. If an I/O device has a transaction queued, the south bridge, in a Round Robin manner, divides the PCI bus for transporting the queued transaction to the corresponding I/O device. As such, each I/O device has separate memory and therefore does not provide a dynamic interface.
In addition to the north bridge receiving transactions from the central processing unit, it may also receive transactions from the video graphics processor and the south bridge relaying transactions from I/O devices. Such transactions have varying requirements. For example, transactions from the central processing unit and video graphics processor are typically high-speed transactions which require low latency. The amount of data in such transactions may vary but is generally a memory line or plurality of memory lines per transaction. The transactions from the I/O devices are generally large amounts of data (i.e., significantly more than several memory lines of data), but are typically latency tolerant.
The central processing unit, the north bridge, the video graphics processor, the south bridge, are fabricated as separate integrated circuits. As such, the transmission path from the central processing unit through the north bridge to the memory is of a relatively significant length, in comparison to buses within the integrated circuits. As is known in the art, the length of a physical path impacts the speed at which data may be transmitted. Such restrictions arise due to the inductance and capacitance of such transmission paths. In short, the relatively substantial lengths of these paths limit the bandwidth capabilities and overall speed capabilities of processing transactions.
Within such a system, the memory includes a memory, such as but not limited to, a dynamic random access memory (DRAM), which is accessed via a single memory bus. If the system requires additional parallel memory, the system employs additional DRAMs and an addition memory bus. But with each additional DRAM bus, the north bridge requires an additional memory controller. Moreover, the north bridge would require a larger overall substrate package to accommodate parallel memory channels. For example, if the system includes four DRAM buses, the north bridge includes four memory controllers. In addition, each device coupled to the north bridge needs to know which DRAM it is accessing such that it provides the appropriate address in the read and/or write transaction.
As illustrated in prior art FIG. 1, the north bridge 100 is electrically coupled to the DIMM 102 via a plurality of external connections 104 to a bus 106, wherein the DIMM 102 connects to the bus 106 across a plurality of pin connections (not shown). The DIMM 102 includes a plurality of memories 108, such as RAM or DRAM, connected to the bus 106 for receiving and transmitting system information across the north bridge 100. The north bridge 100 and the DIMM 102 are connected via the external connections 104 and the bus 106, which produce a plurality of complications. For example, during the manufacturing process, there are additional manufacturing steps associated with the external connections. There are also problems of potential interference or corruption of the data transmitted across the connections 104. Moreover, problems arise due to space restrictions within modern computing systems as the DIMM 102 consumes valuable real estate within a computer processing system. And, among other things, having the DIMM 102 externally connected to the north bridge 100 reduces overall system speed as the system information must be transmitted across the external connections 104, thereby increasing processing times and reducing overall system efficiency.
With further developments of memory devices, a previous approach to reducing problems associated with external placement of memory was to place a frame buffer associated with a graphics processor on a north bridge integrated circuit for storing graphics information. This previous approach teaches solely of a graphics memory buffer for interaction with the graphics processor, but does not address complications that arise with respect to system instructions. Moreover, the frame buffer consisted of a memory storage size, in bytes which is wholly inadequate for modern processing requirements, which would render it almost useless for storing system instructions. Moreover, the previous approach would be unable to include adequate system memory without thereupon producing an extremely large integrated circuit, inconsistent with a standard dimension integrated circuit, which would be practically unusable in modern computing systems due to the size of the memory devices at that time.
Therefore, there exists a need for an improved integrated circuit having including at least one system memory integrated with the information router for the improved processing of system information and to provide dual channel bandwidth with a single channel package size.